1. Field of the Invention
The present invention relates to the field of computers and particularly to computer systems that operate in accordance with the IBM ESA/390 architecture and particularly to computers that have communication among units that form the computer system.
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2. Description of the Related Art
In prior art systems, units communicate using a number of different communication methods. For example, there is one method for handling interruptions and yet another method for handling work requests sent from one unit to another.
In general, computer systems can be described as having two layers of architecture, an outer layer and an inner layer. The outer layer is the architectural layer which is defined, for example, in a specification such as the Principles of Operation (POO) for the IBM Extended System Architecture (ESA)/390. Viewed at the outer layer, an interruption is an unexpected transfer of control. Viewed at the inner layer, the details of how the interruption is processed are seen. Many interruption requests may exist concurrently in a computer system. The inner layer must maintain a list of interrupt requests that are pending, so they may be processed in order. Typically, the inner layer sets interrupt requests in an interrupt register as they arise and clears the requests as they are serviced.
Many different interruptions are generated by different modules or functions in a computer system. Typically, different classes of interruptions are defined such as External, Input/Output (I/O), Machine Check, Program, Supervisor Call, and Restart interruptions. Typically, for a particular interrupt request, a corresponding particular interrupt signal is used to set a corresponding particular interrupt bit location in an interrupt register. Also, typically an interrupt mask is used so that certain unwanted interrupt requests are masks from being processed by the interrupt priority encoder. The priority encoder examines the unmasked pending interrupt requests to determine which one has the highest priority and hence which one needs to be serviced next. After the interruption is serviced, the appropriate bit location in the interrupt register is cleared by the hardware.
In prior art systems, once an interrupt request bit is set, control software was not permitted to reset it. The interrupt requests are reset only as a part of a general CPU Reset or as part of an IPL (Initial Program Load).
In prior art systems, interruptions generated by exceptions detected in the software use a different communication method than interruptions generated by hardware. Often there are conflicts in assigning priorities among hardware and software interruptions and consequently, priority encoders have difficulty determining the order that interrupt requests are to be processed. Also, destination units for interrupts in the prior art have serviced the interrupt requests with a fixed order and did not accept any different order thereby limiting the flexibility of the computer system.
In some implementations, interruptions are lost due to the high frequency of the events generating the interrupt requests or due to the low frequency of sampling of the interrupt requests by the priority decoder. Also, if the interruption handler fails, interrupt requests are often lost.
In accordance with the above background, there is a need for improved communications methods in computer system.